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integrated silicon solution, inc. www.issi.com 1 rev. a 11/08/2011 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat- est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances is61wv2568edbll is64wv2568edbll features ? high-speed access time: 8, 10 ns ? low active power: 85 mw (typical) ? low standby power: 7 mw (typical) cmos standby ? single power supply v dd 2.4v to 3.6v (10 ns) v dd 3.3v 10% (8 ns) ? fully static operation: no clock or refresh required ? three state outputs ? industrial and automotive temperature support ? lead-free available ? error detection and error correction 256k x 8 high speed asynchronous cmos static ram with ecc description the issi is61/64wv2568edbll is a high-speed, 2,097,152-bit static rams organized as 262,144 words by 8 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with inno- vative circuit design techniques, yields high-performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be re- duced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe. the active low write enable (we) controls both writing and reading of the memory. the is61/64wv2568edbll is packaged in the jedec standard 44-pin tsop-ii, 36-pin soj and 36-pin mini bga (6mm x 8mm). functional block diagram december 2011 m e mo ry a rra y ( 256 k x 8 ) ecc a rra y ( 256 k x 4 ) d e c o d e r i / o d a t a circ u it ecc co l u m n i / o 8 8 1 2 8 4 co n t ro l circ u it /ce /o e /w e i o0 - 7 a 0 - a 1 7
2 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll pin configuration 36 mini bga pin descriptions a0-a17 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 bidirectional ports v dd power gnd ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a0 a1 a2 a3 a4 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc a17 a16 a15 a14 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a13 a12 a11 a10 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc a0 a1 a2 a3 a4 ce i/o0 i/o1 v dd gnd i/o2 i/o3 we a5 a6 a7 a8 a9 nc nc nc nc nc a17 a16 a15 a14 oe i/o7 i/o6 gnd v dd i/o5 i/o4 a13 a12 a11 a10 nc nc nc nc 44 43 42 41 44-pin tsop (type ii) 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd v dd i/o6 i/o7 a9 a1 a2 oe a10 nc we nc nc ce a11 a3 a4 a5 a17 a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 v dd gnd i/o2 i/o3 a14 36-pin soj
integrated silicon solution, inc. www.issi.com 3 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd C0.5 to v dd + 0.5 v v dd v dd relates to gnd C0.3 to 4.0 v t stg storage temperature C65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. error detection and error correction ? independent ecc with hamming code for each byte ? detect and correct one bit error per byte ? better reliability than parity code schemes which can only detect an error but not correct an error ? backward compatible: drop in replacement to current in industry standard devices (without ecc) truth table mode ce we oe i/o operation v dd current not selected h x x high-z i sb 1 , i sb 2 (power-down) output disabled l h h high-z i cc read l h l d out i cc write l l x d in i cc operating range ( v dd ) 1 r ange ambient temperature is61wv2568edbll is64wv2568edbll v dd (8, 10 n s ) v dd (10 n s ) industrial C40c to +85c 2.4v-3.6v (10ns) 3.3v 10% (8ns) automotive (a1) C40c to +85c 2.4v-3.6v automotive (a3) C40c to +125c 2.4v-3.6v note: 1. contact sram@issi.com for 1.8v option
4 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll power supply characteristics (1) (over operating range) -8 -10 -20 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. 40 30 25 ma supply current i out = 0 ma, f = f max ind. 45 35 30 auto. 50 45 typ. (2) 21 21 i cc 1 operating v dd = max., com. 20 20 20 ma supply current i out = 0 ma, f = 0 ind. 25 25 25 auto. 40 40 i sb 1 ttl standby current v dd = max., com . 10 10 10 ma (ttl inputs) v in = v ih or v il ind. 15 15 15 ce v ih , f = 0 auto. 30 30 i sb 2 cmos standby v dd = max., com . 5 5 5 ma current (cmos inputs) ce v dd C 0.2v, ind . 6 6 6 v in v dd C 0.2v, or auto. 15 15 v in 0.2v , f = 0 typ. (2) 1.5 1.5 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C1.0 ma 1.8 v v ol output low voltage v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v a c (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 10% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = C4.0 ma 2.4 v v ol output low voltage v dd = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) C0.3 0.8 v i li input leakage gnd v in v dd C1 1 a i lo output leakage gnd v out v dd , outputs disabled C1 1 a note: 1. v il ( min.) = C0.3v dc; v il (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v ih ( max.) = v dd + 0.3v dc; v ih ( max.) = v dd + 2.0v a c (pulse width < 10 ns). not 100% tested.
integrated silicon solution, inc. www.issi.com 5 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll read cycle switching characteristics (1) (over operating range) -8 -10 -20 symbol parameter min. max. min. max. min. max. unit t rc read cycle time 8 10 20 ns t aa address access time 8 10 20 ns t oha output hold time 2.0 2.0 2.5 ns t a ce ce access time 8 10 20 ns t doe oe access time 4.5 4.5 8 ns t hzoe (2) oe to high-z output 3 4 8 ns t lzoe (2) oe to low-z output 0 0 0 ns t hzce (2 ce to high-z output 0 3 0 4 0 8 ns t lzce (2) ce to low-z output 3 3 3 ns t pu power up time 0 0 0 ns t pd power down time 8 10 20 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. ac test loads figure 1. 319 5 pf including jig and scope 353 output 3.3v figure 2. z o = 50 1.5v 50 output 30 pf including jig and scope ac test conditions parameter unit (2.4v-3.6v) input pulse level 0.4v to v dd -0.3v input rise and fall times 1v/ ns input and output timing v dd /2 and reference level (v ref ) output load see figures 1 and 2
6 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) (ce and oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2) (address controlled) (ce = oe = v il ) data valid read1.eps previous data valid t aa t oha t oha t rc d out address
integrated silicon solution, inc. www.issi.com 7 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll write cycle switching characteristics (1,3) (over operating range) -8 -10 -20 symbol parameter min. max. min. max. min. max. unit t wc write cycle time 8 10 20 ns t sce ce to write end 6.5 8 12 ns t aw address setup time 6.5 8 12 ns to write end t ha address hold from write end 0 0 0 ns t sa address setup time 0 0 0 ns t pwe 1 we pulse width 6.5 8 12 ns t pwe 2 we pulse width (oe = low) 8.0 10 17 ns t sd data setup to write end 5 6 9 ns t hd data hold from write end 0 0 0 ns t hzwe (2) we low to high-z output 3.5 5 9 ns t lzwe (2) we high to low-z output 2 2 2 ns notes: 1. test conditions and output loading conditions are specifed in the ac test conditions and ac test loads (figure 1). 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. shaded area product in development
8 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll ac waveforms write cycle no. 1 (1,2) (ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
integrated silicon solution, inc. www.issi.com 9 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps write cycle no. 2 (1,2) (we controlled: oe is high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
10 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll data retention waveform (ce controlled) high speed data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 3.6 v i dr data retention current v dd = 2.0v, ce v dd C 0.2v com. 0.5 5 ma ind. 6 auto. 15 t sdr data retention setup time see data retention waveform 0 ns t rdr recovery time see data retention waveform t rc ns note 1: typical values are measured at v dd = v dr (min), t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode
integrated silicon solution, inc. www.issi.com 11 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll automotive (a1) range: -40c to +85c speed (ns) order part no. package 10 is64wv2568edbll-10ba1 36 mini bga (6mm x 8mm) is64wv2568edbll-10bla1 36 mini bga (6mm x 8mm), lead-free is64wv2568edbll-10cta1 tsop (type ii), copper leadframe is64wv2568edbll-10ctla1 tsop (type ii), lead-free, copper leadframe IS64WV2568EDBLL-10KLA1 400-mil plastic soj, lead-free automotive (a3) range: -40c to +125c speed (ns) order part no. package 10 is64wv2568edbll-10ba3 36 mini bga (6mm x 8mm) is64wv2568edbll-10bla3 36 mini bga (6mm x 8mm), lead-free is64wv2568edbll-10cta3 tsop (type ii), copper leadframe is64wv2568edbll-10ctla3 tsop (type ii), lead-free, copper leadframe is64wv2568edbll-10kla3 400-mil plastic soj, lead-free ordering information industrial range: -40c to +85c speed (ns) order part no. package 8 is61wv2568edbll-8bli 36 mini bga (6mm x 8mm), lead-free is61wv2568edbll-8tli tsop (type ii), lead-free is61wv2568edbll-8kli 400-mil plastic soj, lead-free industrial range: -40c to +85c speed (ns) order part no. package 10 is61wv2568edbll-10bi 36 mini bga (6mm x 8mm) is61wv2568edbll-10bli 36 mini bga (6mm x 8mm), lead-free is61wv2568edbll-10ti tsop (type ii) is61wv2568edbll-10tli tsop (type ii), lead-free is61wv2568edbll-10kli 400-mil plastic soj, lead-free
12 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline
integrated silicon solution, inc. www.issi.com 13 rev. a 11/08/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61/64wv2568edbll note : 5. reference document : jedec spec ms-027. 1. controlling dimension : mm at the seating plane after final test. 3. dimension b2 does not include dambar protrusion/intrusion. 4. formed leads shall be planar with respect to one another within 0.1mm 2. dimension d and e1 do not include mold protrusion . 12/20/2007
14 integrated silicon solution, inc. www.issi.com rev. a 11/08/2011 is61/64wv2568edbll note : 1. controlling dimension : mm . 2. reference document : jedec mo-207 08/12/2008 package outline

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